资源列表
canbus
- 此例参照SJA1000CAN通信控制器，通过CAN总线控制器完成CAN总线的通信协议。所传文件为CAN总线的VERILOG代码。-This reference SJA1000CAN communication controller, to complete the communication protocol of CAN bus through the CAN bus controller. The transfer document for the CAN bus VERILOG code.
divide_7
- 七分频 quartus实现 有RTL图-RTL implementations seven frequency quartus map
fpgacis
- 主要是通过使用FPGA利用CIS（接触式图像传感器）进行图像采集，通过AD转换之后把数据存储到FPGA里面开辟的FIFO-Mainly through the use of FPGA utilization of CIS (non-contact image sensor) image acquisition, through the data storage after AD transform to open the FIFO FPGA inside
I2C_wr(no-down)
- I2C的读写时序，希望有帮助，写的很辛苦当时-I2C read and write timing, want to help, write a very hard time
lab5_doc
- FPGA很好的实验代码，用verilog进行编写的！-FPGA，used verilog HDL！
ALU
- 简单在fpga上实现的alu部分功能，初学数字信号处理者使用-Simple on fpga alu implemented some functions, beginner to use digital signal processing
bch_dec_enc_dcd
- 关于BCH的编码器和译码器，可实现16位，32位，64位，128位的编码和译码纠错，2位纠错，Verilog实现-On the BCH encoder and decoder, can achieve 16-bit, 32-bit, 64-bit, 128-bit encoding and decoding error correction, 2-bit error correction, Verilog implementation
aes-project-master
- aes project vhdl FPGA
xitong1
- 一款基于FPGA的对于VGA实现全彩控制的程序-A FPGA-based implementation for the full-color VGA control procedures
QuartusIITimequest
- 关于quartus中的Timequest Timing analyzer的讲解PPT，由Altera提供-About quartus in Timequest Timing analyzer' s explanation PPT, provided by the Altera
VHDL实现3-8译码器
- VHDL实现3-8译码器,使用VHDL硬件描述语言，实现简单的3-8译码器等功能。
verilog
- 数字信号处理的FPGA实现第三版（Meyer-Baese）书上的所有例程-All the routines in the book of digital signal processing FPGA Implementation of the third edition (Meyer-Baese)