资源列表
16f630
- hi impedance remote control ir circuits
EXPT12_5_RSV
- 采用高速A/D的存储示波器设计，quartus2平台-high-speed A / D to the storage oscilloscope design, platform quartus2
fft_ug
- altera的FFT IP核的用户手册，介绍了如何使用ALTERA IP核生成FFT核，如何设置参数并讲述了如何仿真，适用于通信方面的FPGA设计工程师，学生。-altera' s FFT IP core user manual describes how to use the ALTERA IP core generated FFT core, how to set parameters and describes how to simulate, for communications, FP
digital-clock
- VHDL语言的数字时钟的设计，用于FPGA的数字时钟的设计。-VHDL language digital clock design, FPGA for digital clock design
EGPWS
- INTEGRATION OF EMERGENCY LOCATOR TRANSMITTER (ELT) OF AIRCRAFT WITH THE GLOBAL POSITIONING SYSTEM (GPS)RECEIVER - A VLSI DESIGN APPROACH
sdram_2port_FPGA
- fpga verilong 带sdram读写 数码管显示 简单易学-fpga verilong
smii_latest.tar
- SMII接口的mac控制器，通过测试。使用verilog语言！-The Serial Media Independent Interface, SMMI, is a low pin count version of the MII normally used between ethernet MAC and PHY. The Serial Media Independent Interface (SMII) is designed to satisfy the following r
seqdet
- 用verilog鉴定10010序列，用verilog鉴定10010序列-10010 sequence identification using Verilog with Verilog identification sequence 10010
Lamp---four2
- FPGA verilog语言编写 通过拨码开关SW0-1控制四种不同流水方式-FPGA verilog language programming DIP switch SW0-1 control four different water way, and can set the starting light
eetop.cn_ISCAS89(verilog)
- ISCAS89测试基准电路，verilog编写，可用于测试向量的生成(iscas89 benchmark, written in verilog language, can be used to generate test pattern)
CodedLOCK
- 基于FPGA的电子密码锁设计与实现，语言是VHDL语言，有注释-FPGA-based design and implementation of electronic locks, language is VHDL language, annotated
DIGITAL-PID
- Use verilog language design DIGITAL-PID source