资源列表
xujiance
- 设计一个序检测电路，功能是检测出串行输入数据Data中的4位二进制序列1101（自左至右输入），当检测到该序列时，输出Out为1；没有检测到该序列时，输出输出Out为0，要求： （1）用状态机方法设计； （2）用Verilog HDL语言设计，用Modelsim软件做功能仿真。(A sequence detection circuit is designed to detect the 4 bit binary sequence 1101 in the serial input data D
vhdl
- 应用vhdl在实验箱上实现键盘扫描带有去抖并且移位(To realize the keyboard scan to shake and shift)
AHB_LITE
- AHB_Lite 通信协议的FPGA Verilog 设计(AHB_Lite communication protocol Verilog design in FPGA)
uart
- FPGA Verilog设计UART通讯程序(UART communication code with Verilog in FPGA)
APBL
- APBL通信协议的FPGA设计，适用于高速通讯(APBL communication protocol FPGA verilog design)
Package for AES-128
- Block mode related AES Package
AES 128 ECB Encryption
- Block mode related AES-EBC Decryption
AES 128 ECB Decryption
- Block mode related AES-EBC Encryption
AD常用库
- altium designer 常用库大全，包含3D库(the most popular lib about altium designer which includes the 3d lib, pcb lib and sch lib)
VHDLwork
- 几个示例程序 用于初学者学习 比如计算器 停表之类程序(Several sample programs are used for beginners to learn)
dds
- 基于DDS的信号源设计（包括三角波、正弦波、方波）(Design of signal source based on DDS)
exp1
- vhdl xinhao,..............