资源列表
project_zyg
- 利用HC——SR04的超声波模块与EGO1板子外加一个EMAX电机形成一个测距报警器 上传文件为vivado程序(Using the HC - SR04 ultrasonic module and the EGO1 board plus a EMAX motor to form a range finder to upload the file as the vivado program)
《HELLO FPGA》-项目实战篇-V1.1版
- 各种实例的FPGA实现，对学习FPGA有一定的帮助，希望大家能够采纳。(The FPGA realization of the digital clock has some help for learning FPGA, and I hope you can adopt it.)
ef48dc75a9a60030c622898a19b0f2d6 (1)
- 内有关于循环码的编码器的程序语言，可用quartus ii打开(There is a program language on the encoder of the loop code, which can be opened with Quartus II)
帧同步
- 这是一个可以实现帧同步的编码，应用verilog编码(This is a coding that can implement frame synchronization, using Verilog coding)
verilog
- 里面包括乘法器等多个verilog编码整理，大多数的编码应该都在内(It includes multiple Verilog coding collation, such as multiplier, and most of the codes should be included)
natebege-0.2.0.tar
- wishbone vhdl config tool
miniuart-1.0.0.tar
- wishbone uart controller
vhdlspp-2.0.1.tar
- vhdl library for configuration
wb_counter-1.0.1.tar
- wishbone counter for fpga
wb_handler-1.0.1.tar
- wishbone ctrl for fgpa - wb handler
counter
- counter by implementation vhdl
lcd
- lcd controler by vhdl