资源列表
reg_bank
- A register bank with the function of output=input when enable is true. Also having a reset function
counter
- A 4 bit counter. In the testbench I combine three counters into one. Verilog codes with testbench.
counter
- 利用vhdl语言实现从0到99的记数功能,并在数码管上进行显示-using vhdl,to count from 0 to 99 and show them on the digital tube.
beep
- 利用vhdl语言控制蜂鸣器发出指定频率的音律.-by means of vhdl ,to tell us how to control beeper to produce designated frequencies sounds.
divfreq
- 利用vhdl语言,说明分频程序的工作原理与流程,并结合led进行显示说明其分频效果.-tell us how to divide frequency from main signals via vhdl,and combine with leds to show us detailed information.
Xilinx_Workshop-Design_Primer
- Xilinx 大学计划Professor Workshops系列课程-Xilinx Workshop FPGA Digital System Design Primer one
mu_12channel
- 适用于IEC61850-9-1的合并单元的程序（VHDL），12个通道。-The software is developed for merging unit under IEC61850-9-1 protocol,12 channels.
AD976_6channel
- 软件是适用于FPGA的VHDL程序，目的是用于满足IEC61850－9协议的电子式互感器采样，软件采用的是AD976芯片，能同时进行6个通道的采样。-The software is based on vhdl for FPGA,which is used for electronic transformer fulfil IEC6185-9 protocol.the AD chip is AD976,it works at the state of 6 channels at the same
QPSK_T
- QPSK解调器的FPGA实现，VERILOG源码-FPGA implementation of QPSK demodulator，VERILOG source
QPSK_R
- QPSK的FPGA实现，QPSK的调制实现-FPGA implementation of QPSK QPSK modulation to achieve
sdram_48LC16M16A
- 48LC16M16A型SDRAM芯片的FPGA控制器程序-48LC16M16A SDRAM chip FPGA controller program
vga_pic_70
- VGA控制程序，光栅图像选择性输出，主要是VGA的控制-VGA control program, a raster image of the selective output, mainly the control of the VGA