资源列表
Dm9000a_Init
- DM9000网口通信芯片控制模块，基于FPGA的控制模块，实现初始化，数据发送接收-The DM9000 network port communications chip control module, FPGA-based control module initialization, sending and receiving data
uart_tx_rx_baudselct
- 使用verilog语言设计的一个uart的源码，可以进行波特率选择。-A uart source code using Verilog language design, baud rate selection.
SDcard
- 一个能用SPI模式的SD读卡程序(VHDL)-A SD card reader program can use SPI mode (VHDL)
FPGAdigital-tube
- 单个按键控制四位数码管，按下去，一直按着，数码管显示数字从小到大递增，松开按键，数字实现递减。-Single button control four digital tube, press down, hold down the digital display figures from small to large increments, release the button, digital implementation decreasing.
The-D-flip-flop
- D触发器的Verilog硬件语言实现，开发环境是ModelSim-The D flip-flop of the Verilog hardware language development environment is ModelSim
4-to-1-digital-selector
- 4选1数字选择器的Verilog硬件语言实现，开发环境是ModelSim-4 to 1 digital selector Verilog hardware language development environment ModelSim
38-decoder
- 3-8译码器的Verilog硬件语言实现，开发环境是ModelSim-The 3-8 decoder Verilog hardware language development environment is ModelSim
decoder
- Verilog编写数字编码器，还有激励输入的代码-Verilog prepared encoder, as well as excitation input code
divider
- Verilog语言编写分频器，用于数字竞赛式抢答器的设计模块之一-The Verilog language divider for digital contest Responder design module one
bitsynchro
- 自己写的位同步实验程序参考，该算法需要发送和接收方的频率比较稳定时，可以很快地达到位同步，且十分稳定。位同步是通信技术的基础之一，希望对大家学习有所帮助。-The program is a reference used for bitsynchro writed by myself.When the both send s and receive s frequency are stable,the program can reach bitsynchro fastly.
lab3_files
- 基于FPGA 计数器的分析及源代码 和怎样写testbench-FPGA counter-based analysis and source code, and how to write testbench
lab7_supplemental_files
- 基于FPGA PS2 的讲解及应用以及举例的大量源码-Based on the interpretation and application of FPGA PS2 as well as the example of a large number of source