资源列表
tse_datapath_reference_design
- altera FPGA实现千兆以太网数据通信的程序源代码-altera FPGA Gigabit Ethernet data communication program source code
EXP6
- 基于Verilog 的实现秒表的程序 先要安装Quartus II 6.0 可用看到时序仿真-To achieve a stopwatch program Verilog to install Quartus II 6 can be used to see the timing simulation based on
1
- 2选1 Verilog 语言的编程 环境是Quartus II 6.0 -2 choose 1 Verilog language programming environment is Quartus II 6
verilog
- 全数字锁相环的verilog源代码，用于FPGA开发全数字锁相环-DPLL verilog source code for FPGA development DPLL
100vhdl
- 经典的FPGA例子,适合于初学者使用，包含大量的实例。- classic examples of FPGA
Traffic_Light
- FPGA模拟实现的交通灯控制系统，语言为Verilog，环境为QurtursII，默认情况下按预先设定的时间进行倒计时，支持人工控制模式让某一方向信号灯常亮。信号灯采用LED代替-The FPGA simulation realization of traffic light control system, language, Verilog, environment QurtursII, default preset time countdown, support manual control
Snatch
- 数字电路课程设计题目：抢答器。实现功能：主持人按下开始后才能抢答，否则犯规；一旦有人抢答，其它选手的抢答即被屏蔽；根据回答结果可进行得分加减并可显示到数码管上。-Digital Circuit Design Title: Responder. Function: Moderator press after the start of Responder, or foul once someone answer in other players Responder shall be shielde
SinPout
- FPGA设计中涉及到的速度与面积互换技巧，本工程的代码用Verilog编写，实现功能串行输入并行输出-It comes to speed and area interchangeable FPGA design skills, the project code written in Verilog function serial input parallel output
sick_room_call
- 数字电路课程设计题目：病房呼叫系统的FPGA实现。实现了题目要求：支持呼叫记忆功能，有呼叫优先级，护士值班室可给予病房呼叫响应信号。-Digital Circuit Design Title: FPGA implementation of the ward call system. The subject of the request: support call memory function, call priority, nurse duty room can give the ward c
Pll_prj
- FPGA中PLL模块的测试代码，代码通过例化一个PLL将25MHz系统时钟倍频到50MHz，然后通过两个不同频率时钟控制两个LED灯闪烁，通过闪烁频率可用观察PLL倍频效果-The FPGA PLL module test code, the code by instantiating a PLL to 25MHz system clock frequency doubling to 50MHz, and then by two different frequency clock control
Matrix_Keyboard
- Verilog编写的4x4矩阵键盘扫描代码，可用QurtursII直接打开工程。具体实现的功能为按下按键，数码管可相应显示0、1、...E、F-Verilog prepared 4x4 matrix keyboard scan code and it s directly available in QurtursII . The concrete realization of the function: key is pressed, the digital tube to the corres
code
- 32bits补码加法器，verilog语言的，xilinx公司芯片上运行通过-The 32bits complement adder verilog language, xilinx chip run through