资源列表
Ex22_trafficlight
- 利用vhdl语言在CPLD上开发了一个交通灯模拟的程序代码-Using VHDL language in CPLD developed a traffic simulation program code
binary_adder_subtractor
- binary adder / subtracter in vhdl
snake-game
- 贪吃蛇游戏，用FPGA实现，已经过实验验证，可在液晶屏幕上运行-Snake game, with the FPGA realization, already experimental results show that can run on the LCD screen
EPM240
- CPLD EMP240 程序。包括加法器，LED显示，串口，蜂鸣器，数码管动态显示等功能。-CPLD EMP240 program. Includes adders, LED display, serial port, a buzzer, dynamic digital tube display and other functions.
2ASK
- 2ask调制与解调的源代码，经过测试可用-2ask modulation and demodulation source code is available, tested
FPGA
- fpga 设计全攻略，很好的fpga入门提高资料-the fpga design Raiders, good fpga the Getting Started improve data
Nios-II_ref
- 介绍了niosii开发环境，以及如何使用niosii来开发FPGA-Nios II software development environment, the tools available to you, and the process for developing software.
uart
- 这是我初学FPGA时，经过验证过的一个串口程序，大家可以下载-This is my beginner FPGA, after validation of a serial program, you can download learn
lkl
- 用门电路搭起来的13进制计数器，在7的时候有一个灯显示，初次提交，不对不处请指教-13 binary counter, gate ride up at 7 when a light display, the initial submission, please enlighten wrong not at
final
- 一个32位的cpu设计，实际是verilog语言，只不过pudn上没有verilog的选项，希望能对你有帮助-this is a 32 bit cpu designer project,which use verilog language. Hope it could help u.
INT_DCT
- Verilog HDL语言实现的整数DCT变换模块。其中包括一维和两维的DCT变换模块各一个。该模块都通过硬件仿真以及FPGA实现后的测试，均满足预期的DCT变换功能。-Integer DCT transfer module with Verilog HDL format. The package includes one 1-D and one 2-D DCT transfer module, which all pass simulation and FPGA evaluation.
V5
- xilinxFPGA v5的手册，十分详细，有利于初学者来学习xilinx的FPGA使用方法。-xilinxFPGA v5 manual is very detailed, is conducive to beginners to learn xilinx FPGA use.