资源列表
detector
- 序列检测器，实验题第一题，懂的人都懂得，可以实现对1101的检测，使用状态机-Sequence detector
lcd
- 实现12864lcd显示自己的学号，每个字为16X16格式。-Achieve 12864lcd show their student number, each word 16X16 format.
ISE_lab18
- FPGA experimental program xilinx company s previous software -FPGA experimental program xilinx company s previous software
8255
- 8255IO的verilog描述语言，仅包含模式零，运行正确，经过调试验证。可放心使用-8255IO the verilog descr iption language of, contains only mode zero, properly run, verification after commissioning. Can be assured
SDRAM
- verilogHDL语言编写，简单的FPGA写sdram程序，初学者必备。-verilogHDL language, write a simple FPGA the sdram program, beginners must.
RAM_FIFO
- 双向fifo,但只能实现只读或者只写，同步读写在时序上很难做出好的设计和判断-bidirectional fifo
risc_cpu_619
- 使用verilog语言在fpga上搭建简单的risc_cpu，在cyclone上已经验证-risc_cpu ,verilog ,have passd
SPI-desgn.zip
- 同步串行外设接口，它可以使MCU与各种外围设备以串行方式进行通信以交换信息。传输的数据为8位，在主器件产生的从器件使能信号和移位脉冲下，按位传输，高位在前，低位在后。,Synchronous serial peripheral interface, it can make the MCU with a variety of peripheral devices to communicate in order to exchange information in a serial manner.
frequency_lms.zip
- 控制频率发生的字,改变频率控制字,可改变频率是否发生和可改变频率变化。该程序可以实现GPS接收所需要的控制字,Control the frequency of occurrence of the word, and change the frequency control word can be changed whether the frequency of occurrence and can change the frequency change. This procedure can b
PWM
- verilogHDL语言编写，简单的FPGA脉冲程序，初学者必备。-verilogHDL language, a simple FPGA pulse program, beginners must.
ISE_lab15
- 以前的xilinx公司的软件的FPGA的实验程序-FPGA experimental program xilinx company s previous software
divide
- 实现带符号位的除法，使用二进制的左移处理，属于第三个大作业，懂的人都懂得-signed divide