资源列表
uart_txd_rxd.zip
- 将接收到的并行数据转换成串行数据来传输。消息帧从一个低位起始位开始，后面是5~8个数据位，一个可用的奇偶位和一个或几个高位停止位。接收器发现开始位时它就知道数据准备发送,Converting the received parallel data into serial data to transmit. The message frame from a low start bit is followed by 5 to 8 data bits, parity bit, and one of th
costable.zip
- cos_table主要应用在GPS接收机中，通过quartus9.1 的编程实现，控制接收的程序,cos_table main application in the GPS receiver, through the programming of the quartus9.1 implementation, control the received program
can_latest.tar
- CAN原代码，通过修改，可以改写成任何通信-CAN original code, by modifying rewrite any communication
09~chapter-05-lbist
- Slides from "VLSI Test arch" book
jingdaqi
- VHDL编写的一个题目竞答器。在quartus II上验证通过，并且在altera的FPGA上实现-VHDL to write a topic quizzes. Validation through quartus II, and altera the FPGA
traffic_verilog
- 交通灯程序，分为大路小路，小路的车少，装有传感器，小路来车时，大路即为红灯，等小路车走完变绿灯。-Traffic lights program, divided into the main road path, the path of the car less, equipped with sensors, the path to the car, the main road is the red light, the other lane car finish becomes green li
risc_cpu
- RISC_cpu，包括所有的模块与测试文件。是夏宇闻第二版书中的错误均已改正，运行正确后上传，请放心使用。-RISC_cpu, including all modules and test files. Xia Wen error of the second edition of the book have been correct, to run correctly upload, please feel free to use.
freq_counter
- vhdl编写的数字频率计,可用三个频段选择，Quartus II 8.1上测试通过-the frequence counter by VHDL，compiled by Quartus II
UartRecv
- verilogHDL语言编写，简单的FPGA串口程序，初学者必备。-verilogHDL language simple FPGA serial program, beginners must.
05~chapter-03-lfsim
- Slides from "VLSI test" book.
RS(204188)
- RS(204,188)译码器的设计，经典实例，经过验证-RS (204,188) decoder design, the classic instance of proven
booth_multiplier
- 从google上下载到的booth乘法器-booth multiplier