资源列表
VHDL_Ethernet
- VHDL实现的以太网测试仪器，可以根据配置生成各种模式的以太网数据报文，并对接收到的以太网数据进行统计。-VHDL realization of Ethernet test instrument can generate a variety of modes depending on the configuration of Ethernet data packets, and receives Ethernet data statistics.
cummings_final
- 著名verilog培训专家communing写的一个非常好电路逻辑设计的一些规范-Famous verilog training expert communing write a very good circuit logic design specification
motor
- 状态机电路，驱动步进马达的四相控制线圈A、B、C、D。马达向前 的四相控制线圈通电过程为：A-AB-B-BC-C-CD-D-DA-A…,后退的过程为A-DA-D-DC -C-BC-B-AB-A…,输入时钟信号CLK和DIR方向控制端控制马达的前进和后退。 -The state machine circuit, the driving of the stepping motor, the four-phase control coils A, B, and C, and D. The mo
shiyan2
- 串口发送，通过拨码开关表示传输的数据，并在数码管显示发送数据-Serial port to send data transmitted via DIP switch, and send data in digital display
Audio_DAC_FIFO
- terasic的DM9000A模块源码，使用nios2做以太网应用的应该会用到-terasic the DM9000A module source, use nios2 do Ethernet applications should be used
traffic
- 交通灯，可以像日常上火中的交通灯那样实现倒数计时且进行显示指示-Traffic lights, like the traffic lights in the day-to-day lit as countdown displayed instructions
miaobiao
- 秒表的VHDL语言程序，是实验课上一个课程设计，非常正确，非常好用。-Stopwatch VHDL language program is the experimental class curriculum design, very correct, very easy to use.
SDRAM
- SDRAM的verilog程序，很好地程序，希望大家支持-SDRAM verilog program, a good program, I hope you will support
myproject
- 开发环境ISE，使用VHDL语言实现了任意整数分配的分频器，又有一个信号可以控制左转右转的流水等。-Development environment ISE using VHDL language to achieve arbitrary integer assigned crossover, there is another signal control Zuozhuanyouzhuan running water, etc..
dma_ahb
- 挂靠在AMBA2.0的AHB总线上的DMA装置，用于直接发起数据传输。-Anchored the DMA devices the AHB bus AMBA2.0, for initiating data transfer.
1.2-led_change
- verilog代码控制led改变 使用xlinx开发平台-led_change verilog
wireless
- 基于FPGA DE0以及niosII的射频无线发送程序,采用spi接口操作无线模块nrf24l01-To spi interface operation wireless module nrf24l01 of FPGA DE0, as well niosII RF wireless transmitter program