资源列表
SRAM_16Bit_512K
- terasic的DM9000A模块源码，使用nios2做以太网应用的应该会用到-terasic the DM9000A module source, use nios2 do Ethernet applications should be used
pipelined_reconfig_multiplier
- parallel pipeline reconfigurable multiplier
stepmotornios
- Altera SOPC系统和Nios II处理器实现的一个简单的步进电机驱动系统。
ultimate_crc_latest.tar
- CRC循环校验源代码，来源于OPENCOREs,用于数字电路中的错误检验。-CRC Cyclic check source code from the OPENCOREs, the error checking used in the digital circuit.
DDS
- 一个DDS的程序，很有用，可以产生频率可控的正弦波-A DDS program is useful, can produce controllable frequency sine wave
Virtex-5_FPGA_yonghuzhinan
- Virtex-5相关文档，适合于开发初期的了解工作。-Virtex-5 document, suitable for the development of the understanding of the early work.
VHDL_LAPS
- 简化LAPS协议，对发送的数据包进行封装、传输和接收，，包含FCS是对整个LAPS帧进行CRC校验。-Simplify LAPS protocol, encapsulation, transmission, and receiving the transmitted data packet, containing FCS is performed on the entire LAPS frame CRC.
SDRAM-design-FPGA-altera
- SDRAM design FPGA altera-SDRAM design FPGA altera.
STA_plan_routing
- 关于数字逻辑设计中静态时序分析和布局布线相关的资料。-Static timing analysis in digital logic design and layout information.
RS-232
- RS-232发送接受模块，测试好用，满足一般要求-RS-232 transmit and receive modules, easy to use test, meet the general requirements
uart-code-(Verilog)
- uart 源码 Verilog CPLD -uart code Verilog CPLD
ISE_lab14
- 以前的xilinx公司的软件的FPGA的实验程序4-Xilinx company s previous software FPGA experimental program