资源列表
Pipeline-3.zip
- Verilog codes for pipelined processor,Verilog codes for pipelined processor
spi_master_slave
- 同步串行数据传输SPI的源代码，它可配置成主机或者从机，挂在总线上。-Synchronous serial data transmission the SPI--s source code, it can be configured as host or slave, hanging on a bus.
float
- 32位浮点加法器 verilog语言编写-32-bit floating-point adder verilog language
VHDL_pinlvbiao
- VHDL实现数字频率表功能，针对中科大复杂数字系统设计大实验进行功能补充-VHDL digital frequency table for the USTC complex digital systems design experimental functional supplement
FPGAandVerilog
- FPGA的宝贝实践经验，Verilog的编程规范，-Precious practical experience in FPGA Verilog programming specifications
M_code
- m序列实现,里面含verilog代码和教程，适合学习-m code
01-USB
- usb读取，仅供参考，在实际应用中要更改以下数据。-Read usb data
KEY
- 用VHDL语言来实现扫描键盘值，并在数码管上显示-VHDL language to achieve scanning keyboard and display on the digital
vhdl-pipeline-mips_latest
- pip-lined MIPS in vhdl
Pipeline-2.zip
- Pipeline processor verilog components ,Pipeline processor verilog components
chenyu--chengxu
- 利用verilog语言编写的RS232转换到RS485程序，实现总线通信-Verilog language converted to RS485 RS232 bus communication
led_keyscan
- verilog文件写的微动按键拨码开关检测代码-verilog file micro key DIP switch detection code