资源列表
serial_in_vhd_data_conversion.
- signal data conversion,signal data conversion
priority_data_encoder_vhd.zip
- priority data encoder,priority data encoder
HappyBirthday.v
- 基于Virtex-5的Happy Birthday程序 Verilog-Virtex-5-based the Happy Birthday procedures Verilog
VHDL-program
- VHDL实验程序。需要的可以在此基础上修改。-Program VHDL experiment. Need can be modified on this basis.
sdram_mdl
- SDRAM VERILOG源代码 控制读写-SDRAM VERILOG source code control read and write
Verilog-HDL-Digital-Design
- Verilog HDL 数字设计与综合 夏宇闻-Verilog HDL Digital Design and Xia Wen
ex2
- 七段码 练习使用 verilog 源代码-Seven-segment code practice using verilog source code
wishbone
- wishbone接口的设计，在交换机和MAC之间建立wishbone接口-the wishbone interface design, wishbone interface between the switch and MAC
addrcheck
- 对单播地址，多播地址，广播地址进行检查，其中对多播地址的检查用于哈希算法-The unicast address, the multicast address, a broadcast address to be checked, wherein the inspection of the multicast address is used for hashing algorithm
Calculate_module
- 使用Verilog语言编写的计算器，能实现10以下2个数的加法和乘法运算。 -Calculator using Verilog language, number 10 addition and multiplication.
ex1
- johnson 计数器 verilog源代码-johnson counter verilog
ex3
- pll ip核结合七段码 verilog源代码-the pll ip core binding seven-segment code verilog source code