资源列表
dds1
- 通过FPGA实现的，dds数字信号发生器，可产生正弦波，方波，锯齿波，三角波(DDS digital signal generator through FPGA, DDS digital signal generator, can produce sine wave, square wave, sawtooth wave, triangle wave)
fpga很有价值的27实例
- 为fpga初学者设计的基于fpga的27个简单实用的应用实例，(FPGA Application example)
简易数字钟
- 基于basys3的简易数字钟，可用于vivado开发环境入门，功能有计时和显示模块。(Basys3 based simple digital clock, vivado development environment can be used for entry, function, timing and display module.)
clock
- 基于verilog简易数字钟，能够做到计时，闹钟，倒计时等功能。(Based on Verilog simple digital clock, can achieve time, alarm clock, countdown and other functions.)
jtag fsm
- jtag接口的状态机实现，李庆华《通信IC设计》随机代码(State machine implementation of JTAG interface)
3des_vhdl
- 3DES VHDL SOURCE CODE
usb_veriloghdl
- USB是 FPGA设计，verilog语言实现(USB is FPGA design, Verilog language implementation)
定点乘法器设计
- 讲解FPGA逻辑设计的乘法器设计方法，优化逻辑资源(Explain the multiplier design method of FPGA logic design and optimize logic resource)
I2C总线协议中文版PDF
- fpga的I2C设计文档，VERILOG语言，I2C协议(FPGA I2C design documents, VERILOG language, I2C protocol)
UART-Altera
- 使用Atera FPGA CycloneII 实现串口通信，遵循RS232协议。FPGA上的模块实现了数据的接收，取补码和发送。(Achieve serial communication with FPGA, following the protocol of RS232.)
xapp1052
- ML605开发版 生成IP核的时候选择250MHZ pcie2.0 X4 5Gb/s 其他参考PDF文档。(When the ML605 development version generates the IP kernel, select 250MHZ pcie2.0 X4 5Gb/s Other reference PDF documents.)
f32c-master
- FPGArduino源码，f32c：VHDL的MIPS和RISC-V指令集实现(FPGArduino source code, f32c:VHDL MIPS and RISC-V instruction set implementation)