资源列表
2010-2011EDAdesign
- 这学期的课程设计安排，急需在本站下载点东西，不然不能回去过年了啊。-这学期末的课程设计，急需下载这个，请允许下载。
YS6
- 这个是伊苏六的攻略……非常全也不知能不能用-Ys VI Raiders this is ... ... not a very wide knowledge can not be used
my_simul
- s2 memory file written in vhdl
4v2
- ENTITY maj IS PORT(a,b,c : IN BIT m : OUT BIT) END maj --Dataflow style architecture --Behavioural style architecture using a look-up table ARCHITECTURE using_table OF maj IS BEGIN PROCESS(a,b,c) CONSTANT lookuptable : BIT_VEC
5vadderN
- 第一次上传资料 关于vhdl，不同的变成风格 初学者，希望多多学习-entity adderN is generic(N : integer := 16) port (a : in std_logic_vector(N downto 1) b : in std_logic_vector(N downto 1) cin : in std_logic sum : out s
dianziqin
- 实现电子琴电子设计自动化的功能，利用数控分频器设计硬件电子琴，当按下琴键时，扬声器发出该琴键相对应的音阶，同时数码管显示音阶数字，若为高音时，二极管点亮。
led
- 在Xilinx开发板上实现两个led数码管从0到99按秒来计数的实验。-In the Xilinx development board implements two led digital tube from 0 to 99 seconds to count by experiment.
EDA_design
- 交通灯的设计，对于红绿灯的交替秒数等功能实现的设计
zdsh
- 用硬件描述语言写的几个自动售货机代码，有对应测试文件，当有硬币投入时，仿真波形得到正确结果。-Hardware descr iption language code written in a few vending machines, has a corresponding test file, when a coin, the simulation waveform to get the right results.
vergleiche
- 32为比特数据比较器，讲高电平位不断右移，直到左边全为0，右边全为1-32-bit data for the comparator, high-bit been right about, until the whole left side is 0, the right of all to 1
counter
- 不同频率的两个计数器，第一个计数器向上技术，第二个当第一个计满后向下计数-Two different frequency counter, a counter up the first technical, the second when the first after the expiration of a count down
statemaschine
- 5状态状态机，1为计数器，2为锁存器，3为向上加一，4为向下减3,5为停止技术在输出为10的时候-5 state state machine, 1 counter, latch 2, 3 plus one up, 4 down to minus 3,5 to stop technology, when the output is 10