资源列表
VHDLcircuitdesign
- 《VHDL电路设计技术》，对于VHDL语言爱好者来说是一本很不错的参考资料！欢迎下载！-《VHDL circuit design technology》， VHDL language for lovers is a very good reference! Welcome to download!
DS18B20ss
- 使用fpga硬件语言写的DS18B20程序，altera的fpga，单总线测试可用-altera fpga ds18b20
IFFT
- ifft 的verilog程序，最好在ISE9.2的平台上实验-ifft the verilog program, the best experimental platform in ISE9.2
fifo
- 高性能设计中常用的fifo模型，采用单端读取数据的方式，数据的位宽以及fifo的深度可以设置。通过modelsim仿真-Fifo design commonly used in high-performance models, using single-ended way to read data, the data bit width and the depth of the fifo can be set. Modelsim simulation by
UART
- UART发送verilog源码，波特率115200，以及testbench源码-Send verilog source UART baud rate 115200, and testbench source
microwave
- 这是用VHDL语言编译的微波炉控制器的源程序，供大家参考。其中包括扫描显示、计数器等部分。-This is compiled with VHDL, microwave oven controller of the source, for your reference. These include scanning display, counters and other parts.
12.4Uart
- 最简单的verilog串口发送接收源代码,已经上机调试,请放心,直接使用-Simple transmit and receive serial verilog source code, has been on the machine commissioning, please rest assured, direct use
7_1LVDS_serilizer
- 7:1LVDS编码 为LVDS方面需求的人提供参考设计，很高兴- This VHDL or Verilog source code is intended as a design reference which illustrates how these types of functions can be implemented. It is the user s responsibility to verify their design for consistency a
PRINTBMP
- 用于设置显示电脑的SVGA模式，及各个色彩寄存器，来显示输出BMP 图像-to set model of SVGA and register to output the BMP image
FIRandMATLAB
- FIR数字滤波器的MATLAB设计与DSP实现-FIR and MATLAB
wangshibo
- 运算器，设计一个4位的算术逻辑单元能够进行下列运算：加法、减法、加1、减1、与、或、非和传递。-yunsuanqi
ADCData
- ADC Interface to read into FPGA