资源列表
clock
- FPGA时钟，vhdl，带设置时间，暂停，开始-FPGA clock
lift
- 运用VHDL实现可控三层电梯 利用LED和点阵表示电梯的上下 与楼层显示-Use VHDL to achieve controllable three elevator use of LED and dot matrix, said the elevator up and down the floor display
good
- 信号发生器，产生可调pwm信号，和可控的四路环路信号-singal merch
FreeARM7_intro
- 用VHDL硬件描述语言实现ARM7软核处理器的功能-ARM7 soft-core implementation with VHDL
sff_a
- HDL example source code 4/5 sff_a
fsm
- verilog四状态状态机 带异步清零端和测试向量 mealy型状态机 很好用哦 -verilog four state machine with asynchronous clear end and test vectors mealy-type state machine oh well
shuzishizhong
- 本实验实现一个能显示小时，分钟，秒的数字时钟。数字时钟-The experimental realization of a can display hours, minutes, seconds, the digital clock. Digital Clock
clock
- 数字时钟的verilog程序，在alteral ep2c5t144调试成功-Digital clock verilog program
12
- 用Verilog语言编写的数字时钟程序-Using Verilog language digital clock procedures!!!!!!!!!!!!!!!!!!!!!!!
afb41325-6770-4395-a6e9-cc248fce9d2c
- 自己设计的，电子出租车计价器，看看有没有什么问题
mul8b
- 有VerilogHDL编写的8位乘法器，可以综合。-Have been prepared in 8-bit multiplier VerilogHDL can be integrated.
61EDA_B365
- 乒乓球游戏电路设计 VHDL eda技术 课程设计-VHDL eda table tennis game circuit design course design