资源列表
ditong
- 低通滤波器ewb设计图,低通滤波器ewb设计图-Ewb design low-pass filter, low pass filter ewb design
ExampleCode_DDS_ADIS16355Driver
- 在keil c开发环境下,采用C语言编写的对ADIS16355惯性测量单元的测试程序,希望能有所帮助-In keil c development environment, written using C language on the ADIS16355 inertial measurement unit testing procedures, hoping to help
EECS_140_VHDL_Tutorial
- Fundamentals of VHDL Programming
cad08
- vhdl coding for and gate
UART
- UART发送verilog源码,波特率115200,以及testbench源码-Send verilog source UART baud rate 115200, and testbench source
dds_quicklogic-FPGA
- dds_quicklogic FPGA DDS信号源-dds_quicklogic FPGA
dpll_demo
- 一个实现简单的数字锁相环Verilog代码,本人借鉴网上现有的代码后经修改在Cyclone II上调通实现,里面有ModelSim仿真成功的波形图
22269
- 大量的FPGAverilog语言示例源码,可以-A lot of language FPGAverilog example source code, can take a look
ADCINT
- 用EP1C系列FPGA控制ADC0809的程序
lab04
- RTL in Verilog (Vending Machine)
VHDLcounter
- VHDL,四位counter,用Vivado写的,可运行,可模拟,可仿真,可写入硬件里,四个指示灯会每一秒闪一次。
VerilogHDL_advanced_digital_design_code_Ch9
- VerilogHDL_advanced_digital_design_code_Ch9 VerilogHDL高级数字设计源码Ch9
