资源列表
AVR
- AVR IP CORE 可以直接用于工程的开发和 已经通过编译和仿真
ARM_Core
- arm vhdl 源代码，解压后多个文件，经过验证-arm vhdl source code, extract multiple files after the
ARM7_VHDL
- arm7的VHDL开源代码，经过了验证，可以使用-VHDL open core of arm7
des-verilog
- des加密算法的verilog语言的实现-des encryption algorithm to achieve the Verilog language
92977818259a
- 8259a的VHDL源代码 对于8086开发很有用-8259a of the VHDL source code is useful for the 8086 development
divider
- 四位无符号二进制除法器的设计,这是整个的工程文档，应该对大家有用-4 unsigned binary division Design
quad-responder
- 四路抢答器，可供四名选手参加比赛的智力竞赛抢答。选手按下按键后，其他选手按下无效，同时对应的指示灯亮，蜂鸣器发出音响。由主持人控制指示灯和蜂鸣器复位。-Quad Responder, for four players to participate in quiz competition Responder. Press the key players, other players press the invalid, while the corresponding indicator light
This VHDL code pertains to the DCO model
- code.doc C.1 DCO LEVEL 2 This VHDL code pertains to the DCO model descr iption in Section 6.5.5. The entity declaration of the level 2 DCO is between lines 18 and 39. The VHDL generics or elaboration-phase parameter constants are declared between
spi master slave
- SPI master slave (fpga/verilog)
apb_timer.tar
- 是基于apb总线下的timer外设的rtl代码，主要包括apb_timer的master逻辑verilog，以及相应的开发文档，包括寄存器的描述，功能特性等。(RTL code is based on timer peripheral under APB bus, which mainly includes master logic Verilog of apb_timer and corresponding development documents, including the descr
AVR
- 利用VHDL实现AVR，IPcode 的 AVR-VHDL implementation using AVR, IPcode the AVR
CANProtocolControllerIPCoreinVerilog
- 一种基于CAN协议的IP核源代码，用Verilog语言实现-CAN Protocol Controller IP Core in Verilog.