资源列表
dfilter
- 用FPGA实现信道化接收机算法，共256个信道，处理时钟40M，时分复用完成算法实现-FPGA implementation using channelized receiver algorithm, a total of 256 channels, processing clock 40M, time division multiplexing algorithm to complete
AM
- AM信号的调制解调DSP算法，包括原理和应用-AM
boxingfashengqi
- 波形发生器一种数据信号发生器，在调试硬件时，常常需要加入一些信号，以观察电路工作是否正常-A data signal generator, waveform generator, in the debugging of hardware, it is often necessary to add some signal to observe the circuit is working properly
jishuqi
- 各种功能计数器利用数字电路技术数出给定时间内所通过的脉冲数并显示计数结果-Features the use of digital circuit technology a few counters for a given period of time the number of pulses passed by the count and display the results
8weishujusuocunqi
- 位数据锁存器，用于存储数据来进行交换，使数据稳定下来保持一段时间不变化，直到新的数据将其替换。 -8-bit data latch for storing data to be exchanged and the data stabilized for a period of time does not change until the new data to replace it.
FIFO
- FIFO,双端口数据存储器，实现数据先入先出的存储器件-FIFO, dual port data memory, data FIFO memory device
clock
- 时钟发生器，利用系统时钟获得需要的时钟信号-Clock generator, using the system clock to obtain the required clock signals
slave-fifo
- C77C68013 SLAVE FIFO buclk 源码！-C77C68013 SLAVE FIFO buclk source.
cpu
- 组成原理实验~简单cpu的设计~基于EDA环境下的-Composition Theory Experiment Design ~ ~ Simple cpu EDA environment based on
8.12MASKmadebyVHDL
- 利用FPGA实现基带编码源代码，大家有兴趣可以参考啊！-MASK made by VHDL
8051
- 在EP2C5上进行8051单片机的核移植-8051 on the EP2C5 nuclear transplantation
ps2verilog
- 用verilog HDL语言实现的PS2驱动。-PS2 program using Verilog HDL