资源列表
ml510_bsb1_std_ip_ppc440
- 这是Xilinx公司FPGA的标准的基于PowerPC440的IP包底层驱动程序，标准的，很难得。-This is the standard Xilinx, FPGA-based IP packet PowerPC440 the underlying drivers, standard, hard to come by.
ML510_ethernet
- 这是Xilinx公司FPGA ML510的ethernet驱动程序，很不错的，希望对大家有用。-Xilinx, FPGA ML510 is the ethernet driver, very good, and I hope useful.
workspace0823
- 这是我写的基于xilinx公司的virtex5版本fpga的network底层程序，其中是C语言与API混合编程，希望对用得着的兄弟有些帮助。-This is what I wrote based company virtex5 xilinx fpga of the network version of the underlying process, which is a mixture of C programming language and API, the brothers want t
list_ch12_08_dot_top
- VGA synchronization Code (640 x 480). It generetes VGA synchornization with only 3 bit color ang 60 hz refresh rate. The source clock is 50 MHz.
list_ch12_01_vga_sync
- VGA synchronization Code (640 x 480). It generetes VGA synchornization with only 3 bit color ang 60 hz refresh rate. The source clock is 50 MHz.
QuartusII_shuoming
- QuartusII简易操作说明 VHDL 仿真器 利用Quartus II 产生.VHO 和.SDO利用在sim_lib 目录中的APEX20K_ATOMs.VHD 和 APEX20K_COMPONENTS.VHD 文件 Verilog 仿真器 -QuartusII VHDL simulator simple instructions generated by Quartus II. VHO and. SDO use in sim_lib directory APEX20K_
int_div
- 基于VHDL的任意分频模块，利用Quartus II 9.0编译通过，并用示波器观察可行-VHDL-based modules of any division, the use of Quartus II 9.0 compiler, and the possible use of an oscilloscope
dpram_anu
- true dpram with using shared variable
shijianzhong
- 时间钟是设计，主要实现时间的计算和整点报时-goole good
cordic
- cordic的verilog设计，qII实现，比较简单，讲诉了算法的实现过程。-cordic the verilog design, qII implementation, relatively simple complaints about the implementation process of the algorithm.
new_128HZ
- 基于vierlog+maxplusII的频率合成器的设计与实现。比较好的代码。-Vierlog+ maxplusII based frequency synthesizer design and implementation. Better code.
ps2_complex
- 基于verilog的PS口控制程序，比较经典的代码。非常简单-The PS-based verilog port control procedures, more classic code. Very simple. .