资源列表
chuankoumokuai
- 用VERILOG实现的串口RS232自收发模块，以通过板级测试。-RS232 serial port with the VERILOG achieve self-transceiver module, through board-level test.
shuzidianlu
- 基于fpga的数字电路可程设计，一个乒乓球游戏机。可以算人对打，5局三胜-Fpga based digital circuit design process, a table tennis game. Operators who can rally, winning three out of 5
verilogHDL
- verilog HDL 的课件，东南大学的课件，具有学习价值-verilog HDL courseware, Southeast University, courseware, a learning value
duogongneng
- 多功能波形放生器，产生三种波。方波。。j锯齿波。。正弦波 -Release device function waveform, resulting in three waves. Square wave. . j ramp. . Sine wave
keyboard
- 键盘功能的实现，主要用来显示键盘上所恩下的键对应的数字-keyboard
Spartan-3ADSPs
- The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.-The objective of the labs today is
lab_instructions3
- The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.-The objective of the labs today is
lab_instructions2
- The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.-The objective of the labs today is
lab_instructions1
- The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.-The objective of the labs today is
sm
- This example shows how a Sm component is directly coded in VHDL as concurrent statements. The multiplexor is coded as a single "when" statement. "Sm" is mnemonic for subtractor-multiplexor.
snake
- 在数码管上跑的贪吃蛇Verilog 程序-In the digital Verilog programs run on Snake
SystemVerilogAssertion
- SystemVerilog Assertion的应用例子。例子均在Synopsys VCS环境下编译通过。-The uploaded files are examples of Systemverilog Assertions. All of the codes are compiled successfully in Synopsys VCS environment.