资源列表
zhentongbu_VerilogHDL
- 帧同步的VHDL程序源代码，巴克码同步实现。-Frame synchronization of the VHDL source code, Barker code synchronization
Dchufaqi
- D触发器，移位寄存器，二进制转化器的verilog语言程序-D flip-flops, shift registers, binary converter verilog language program
luojidianlu
- 一些复杂逻辑电路的设计，状态机的verilog的程序语言-The design of complex logic circuits, the state machine of the verilog programming language
luojimokuai
- 一些逻辑门，如与非，异或门的verilog的程序语言设计-The number of logic gates, such as non-exclusive OR gate verilog programming language design
vhdl
- 数目很多的VHDL程序集合，简单，复杂的模块都有。-Number of VHDL program a collection of simple and complex module has.
Four-intelligent-responder-
- 四路智能抢答器的VHDL实现，具有开始和复位功能，同时具有答题倒计时功能-Four intelligent responder VHDL implementation, with start and reset function, simultaneously has the answer countdown function
verilogcalculator
- 简易的计算器，可实现加减乘除运算，采用verilog编写-Simple calculator, addition, subtraction operation can be realized using verilog prepared
calculator
- 简易的计算器，可实现加减乘除运算，采用verilog编写-Simple calculator realized by verilog,which could operate addition and subtraction process
clock
- 数字钟，采用电平触发，可以切换显示模式。-Digital clock, trigger level, you can switch the display mode.
screen_1
- 符合avalon总线接口的LED控制软核-Avalon bus interface LED control soft-core
rtl
- Verilog 蜂鸣器唱歌程序 同时可以显示音调大小-The Verilog buzzer singing program
vhdl-programming-by-example
- This book was written to help hardware design engineers learn how to write good VHDL design descr iptions. The goal is to provide enough VHDL and design methodology information to enable a designer to quickly write good VHDL designs and be able to