资源列表
VLSI
- CRC并行16位计算，十分强大，十分好用-CRC parallel 16-bit computing, is very powerful, very easy to use
FPGA-and-DSP-based-on-the-Bayer-format-image-pre-p
- 在图像实时处理的过程中，下层图像预处理的数据量大，运算简单，但是要求运算速率高，可以用FPGA硬件来处理，上层所处理的数据量少，算法结构复杂，适于运算速度快，寻址灵活的DSP数字信号处理器进行处理。该系统充分发挥了FPGA和DSP各自的优势，能更好地提高图像处理的实时性，降低成本。 -Real-time processing in the image process, the lower the amount of data preprocessing, simple operation,
16DIANTIKONGZHI
- 16层电梯控制VHDL程序 内含各个模块的程序-16 floors of elevator control program includes modules in VHDL program
shuzimiaobiao
- 秒表设计中的分块模块的设计，运用VHDL语言编写-Stopwatch design block module design, the use of VHDL language
FinitStateMashine
- implement finit state machine for finding "1010" pattern in a bit stream,there might be several after each other and also use one-hot state in modelsim
alu8bit
- it implement alu for 8 bit addition,subtraction,and ,or, left shift without overflow support and simulate it in modelsim
memory
- DESIGN A SINGLE PORT MEMORY 8*256 using array with standard logic & tri_state gate, and simulate it by reading & writing word
seven_segment
- It is seven segment decoder and display hexadecimal digits, and for wirting with vhdl use PACKAGE-It is seven segment decoder and display hexadecimal digits, and for wirting with vhdl use PACKAGE...
shift_register
- It is noise generator.it is a linear feedback 16 shift-registe where the bits 15,14,12,3 are fed back via xor gates.make random signal close to real noise
new
- four bit shift register verilog code-four bit shift register verilog code
turbo_encoder
- 在赛灵思的FPGA上实现turbo码的编码程序,使用Verilog语言实现。-Implemented on Xilinx FPGA in the turbo coding principle, the use of Verilog language.
Verilog
- 用verilog实现七位最大公约数的算法，使用状态机，可仿真电路图-Seven with the greatest common divisor algorithm verilog implementation, the use of state machine circuit simulation