资源列表
altera_up_avalon_sram
- 基于Avalon的SDRAM控制器IP核-Avalon SRAM Controller
alarm
- 利用vhdl和verilog两种方式可以实现的fpga芯片的数字钟，其中包含多个可设计改动的个性化模块。源代码利用quartusii平台写作，可移植性很强。-Using vhdl and verilog fpga can be achieved in two ways-chip digital clock, which includes several design changes personality module. Source code using the platform quartu
zidong_led_water
- 用Verilog语言实现了将50MHz时钟分频到1Hz，实现了自动流水显示HELLO字母功能-Verilog language of the 50MHz clock frequency to 1Hz, realized the function of automatic water display HELLO letters
BaseGate
- ep2c5 实现 逻辑门 verilog语言，quartus 2 仿真-ep2c5 the realization of logic gates verilog language, quartus 2 Simulation
led_key
- 实现按键控制数码管线功能的FPGA实现，虽然这个程序比较简单，但在这个程序中加入了防抖动功能，值得借鉴。-led_key
Verilog_hw_problem1---Copy
- this is a verilog program for a mealy machine
led1
- 基于FPGA（Verilog HDL）LED灯实验-Leds flashing.
17.SPI-to-SPI
- 很好的SPI程序,调了很久才出的结果，希望对大家有用-Good SPI program, adjusting for a long time before the results, I hope useful
RecoveryUtility
- DE2開發平台USB-BLASTER-EEEPRON-RESET的程式-DE2 Development Platform USB-BLASTER-EEEPRON-RESET program
100vhdl
- 100个学习vhdl的经典例子！
develop_frame_find
- 基于FPGA中OFDM中的帧检测，由于采用简化算法，采用较少的复数乘法器，易于硬件实现，且节省资源，采用verilog实现.-Frame detection based on FPGA for OFDM, a simplified algorithm, using less complex multiplier, easily implemented in hardware, and save resources, the SNR performance is slightly lower th
VHDL-divider-design
- VHDL分频器设计，本文使用实例描述了在FPGA/CPLD上使用VHDL进行分频器设计，包括偶数分频、非50 占空比和50 占空比的奇数分频、半整数（N+0.5）分频、小数分频、分数分频以及积分分频。-VHDL divider design, this article describes use cases, including even divide, non-50 duty cycle and 50 duty cycle odd divider, half integer (N+0-cr