资源列表
RSD
- RSD- rsd source code in vhdl
16bit_pipeline
- 16 bit pipeline design by vhdl.
lab-1.3
- thisi s lab3 from altera
KeyToLED
- 在这个程序中，我们采用了按键控制LED，来熟悉FPGA程序。-in the program ,wo use the key to control the led ,so wo are familiar with the FPGA Program.
RESET_LED_8X8
- VHDL实现8*8点阵显示，实现平台XC3S500E-VHDL implementation of the 8* 8 dot matrix display platform XC3S500E
ALU_DSN
- 算术逻辑部件设计实例，ALU_design，供大家参考。-ALU design example, ALU_design, for your reference.
qpsk_module
- 采用Verilog语言编写了一个qpsk调制的程序-Verilog language using a modulation process qpsk
ALU_design
- 74181alu vhdl设计，欢迎您的下载-74181alu vhdl
johnsonverilog
- 本verilog代码实现了johnson计数器，也就是控制流水灯的程序，具体为从左到右和从右到左以及停止的流水灯操作-The verilog code of the johnson counter, that is, water lamp control procedures, specifically for the left to right and from right to left and stop the flow lamp operation
用LV获取机器CPU和硬盘序列号
- 用LV获取机器CPU和硬盘序列号，labview 8.6版本可以使用-Access to the machine with the LV CPU and hard drive serial number, labview 8.6 version can be used
DiSyLab4
- A simple 8085 cpu design
dem4bit_hienthi
- the verilog source code for being an examble to counts 4-bit number and display in 7-segment.