资源列表
18-divide-8-divider
- 从ASM状态图可以看出，在state=0时，初始化参数，如果开始信号有效则载入被除数与除数，接着进入state=1状态，首先判断被除数寄存器的高九位是否大于除数，如果是则产生溢出信号，并回到此状态；否则被除数寄存器向左移一位，并进入state=2状态，同样先判断被除数寄存器的高九位是否大于除数,如果是则被数高九位减去除，并被除数最后一位置为1，并回到此状态；否则被除数寄存器向左移一位，并进入state=3状态, 同样先判断被除数寄存器的高六位是否大于除数,如果是则被数高九位减去除，并被除数最后一
VHDL_101
- 非常好的vhdl学习代码；a基本且详细的介绍了vhdl的功能； 让你快速学习vhdl-Vhdl code for a very good learning a basic and detailed introduction to the vhdl function allows you to quickly learn vhdl
Stopwatch
- Stop-watch for FPGA on 7 segment display
BCD
- ROM vhdl for binary to BCD
NiosII
- 用CPLD_FPGA实现NiosII嵌入式系统配置技术-Embedded systems with CPLD_FPGA configuration technology to achieve NiosII
desig
- 汽车零部件试验测控平台示波模块的设计Oscilloscope-Oscilloscope measurement and control platform for automotive module design
semafor
- This the code for 2 traffic lights. S1 is a senzor that tells when there are cars waiting and S2 says if people are waiting to cross.-This is the code for 2 traffic lights. S1 is a senzor that tells when there are cars waiting and S2 says if people a
AnalizatorAndCounter
- VHDL counter project fo Altera DE2 Development Board-VHDL counter project fo Altera DE2 Development Board
TestSpeed
- test aplication for Altera DE2 development board
fpga-jianpan-ip-core
- 基于fpga的键盘设计ip核的vhdl源代码-Ip fpga design of the keyboard based on the vhdl source code for nuclear
freedev_ps2
- 自由电子科技的PS2键盘的avalon外设ip core-Free electronic technology avalon PS2 keyboard peripheral ip core
NIOS-II-wuxian-IP
- 基于双NIOS II 的IP 无线收发机_july_3.pdf-NIOS II of the IP based on dual transceiver _july_3.pdf