资源列表
specman
- SPECMAN基本指导，供VERILOG验证工程师使用。-SPECMAN basic guide for verification engineers VERILOG.
Function-Generator
- 函数发生器，ＶＨＤＬ的综合实验 可以产生不同的函数，并将它输出。-Function generator, VHDL comprehensive experiment can have different functions, and output it.
shishi
- 基于FPGA的实时采样系统设计！双口ram典型应用！-FPGA-based real-time sampling system!
equivalent_sample
- 基于FPGA的等效采样系统设计，包含状态机设计，双口ram使用方法，分频设计等-FPGA-based equivalent sampling system design, including the state machine design, dual-port ram usage, frequency design
ceping
- 等精度频率计设计，精确到1/50M之一！-And other precision frequency meter design, accurate to one 1/50M!
FPGA
- 讲述FPGA设计的四种常用思想与技巧,典型分析-About four common FPGA design ideas and techniques
HEX_BCD
- hexa to bcd signal program
DVIaVGA
- 鉴于大家对两者的误解，有必要说明VGA与DVI的根本区别-Given all of the misunderstanding between the two, it is necessary that the fundamental difference between VGA and DVI
Verilog_cpu-_example
- 想用verilog进行CPU搭建的同学过来围观啦~-Want to use verilog for students to build over the crowd CPU 啦 ~
Encoder1
- encode of aes arith" it describer how to encode streams and something.. if you want to acknowlegde about-encode of aes arith" it describer how to encode streams and something.. if you want to acknowlegde about
VHDL-Example-2
- fir filter vhdl code
Filtres
- Module to filter signals