资源列表
ssd
- 一个fpga开发板上的数码管应用,是用verilog编写，已经在开发板上-a SSD practice
calender
- 这是用Verilog语言编写的万年历源代码，其中以小时为最小单位，可以区分闰年。有瑕疵还望海涵。-This is the calendar source code written in Verilog language, which hour is the smallest unit that can differentiate between leap years.
CPU
- 多周期cpu结构有特点，性能优良，便于理解。-This cpu is very good.It is easy to understand.
bysj
- 基于FPGA频率特性仪，随着世界新进水平发展，测试电路频率是重点-FPGA frequency characteristics of instrument，With the development of a new world advanced level, the test circuit frequency is the key
DDS_SOPC
- 介绍了一种基于DDS/ SOPC技术的谐波信号发生器的设计方案, 详细论述了DDS的 工作原理及SOPC的设计过程。在设计中将DDS模块和MCU模块集成到一个单片FPGA上, 使设计出的系统具有集成度高、灵活性好等优点。-This paper presents a design of harmonic signal generator based on DDS/SOPC technology, particularly discussed the principle of DDS a
SAE-J2178_1v002
- OBD II 标准,SAE J2178车辆在线诊断标准,物理层-Standard of ODB II SAE J2178 On-Board Diagnostic,North-American standard.physical layer
FPGAandAT89S52
- 实现单片机与ＦＰＧＡ通信、传输数据、主要用于做ＦＰＧＡ信号发生器-FPGA and AT89SS52
quatus2_example
- 这是一个典型的利用quatus2进行设计的案例，可以让你对quatus2的设计有一个总体的感受！-This is a typical design using the program quatus2 which can help you kown this promgram soon.
Four-adder-and-four--counter
- 4位全加器和计数器的verilog的例程，还有四位全加器的仿真程序。-Four QuanJia device and counter verilog of the routines, and four QuanJia device simulation program.
decoder-realizing-of-FPGA
- 译码器的fpga相应的代码，还有仿真实现。在这里设计的七段数码管显示译码器是采用case语句来实现的。-Decoder fpga corresponding code, and simulation. In the design here seven segment digital pipe display the decoder is the case of the realization of the statements.
NCO-design-based-on-CORDIC
- 基于CORDIC算法的NCOSHIXIAN ,包括软件仿真波形和硬件实现波形对比-NCO design based on cordic algorithm.THis paper dervices the principle of CORDIC algorithm precisely.
sequential-detactor
- 本次例程包括七阶伪随机序列发生器、序列码检测器，奇偶校验器、CRC（循环冗余）校验器，并附有FPGA的代码和仿真。-The routines including seven order pseudo-random sequence generator, sequence yards detector, parity validator, CRC (cyclic redundancy) validator, and with FPGA code and simulation.