资源列表
SGvga
- 基于System Generator 实现Xilinx FGPA的VGA显示模块，板块Nexys™ 3 Spartan-6 FPGA Board，可以直接把.bit文件下进去进行。 具体说明可以参考本人博客：http://www.openhw.org/wenlong0601/blog/12-03/239390_f7ef3.html-Based on the System Generator Xilinx FGPA VGA display module, the plate Nexy
uar_bmp
- 在sopc平台上面，实现电脑通过串口发送彩色bmp格式图片并显示到lcd上面。-a color picture can be displayed in LCD though UART.
CPU
- 十指令简易CPU实现代码，可向外设端口读写数据-ten instruction simply cpu,it can write and read data to other equipment
traffic-light
- 自己编写的用VHDL代码，实现十字路口红绿灯控制。并且能用数码管显示不同灯的显示时间倒计时。-His writing the code with VHDL, realize the intersection traffic light control. And can the digital display different lamp shows the time countdown.
FIFO2
- 用verilog HDL语言编写的fifo存储器源文件 -Using Verilog language HDL FIFO memory source file
digital_clock_top
- vhdl实现数字钟的开发，并在DE-2板子上实现，可调时、调分-VHDL realize the development of digital clock , the platform is DE-2 board,which can Regulation time and minite
oc_i2c_masterI2CIP
- oc_i2c_master 经过验证有效ip核 IIC ip核-oc_i2c_master
SRC
- 流水线cpu 顶层模块verilog源代码，和ALU子模块源代码-Pipelined cpu top-level module verilog source code, and the ALU sub-module source code
POC
- POC is one of the most common I/O modules, namely the parallel output controller. It plays the role of an interface between the computer system bus and the peripheral (such as a printer or other output devices).-A parallel output controller
booth
- BOOTH算法VHDL语言代码 基于FPGA quartus-BOOTH VHDL!
cpu
- 用FPGA实现了CPU中RAM,ROM等功能，设计比较完整-FPGA Implementation of a CPU, RAM, ROM, function, design is more complete
encode
- 实现用FPGA控制编码芯片AHA4013的编码