资源列表
Frecdiv
- Frecuency divisor with 3 bits of variable.
tren_de_pulsos
- Generator of pulse train to 50MHz.
subtractor5
- 5进制减法器 输入时钟信号 和reset信号 输出信号为二进制数-5 hex subtractor
happy5
- 数码管小游戏，让SSD的各个段连续地按照顺时针方向转动，两段重叠片刻-game for ssd: ssd lit up in clockwise
REC_C8
- Altera 的NIOSII一个应用，实现NAND Flash的实时数据记录。-NIOSii CPU
div_fp
- 输入任意频率，可实现实现1-15任意占空比为50 的分频,-Enter any frequency can be realized to achieve the 1-15 arbitrary duty cycle 50 of the sub-frequency
clock
- verilog 电子钟！！！ 用于初学者学习-Electronic clock design Electronic clock design Electronic clock design
cpu-and-ram
- 这是一个用VHDL语言写的简单带存储器的CPU设计，不涉及流水线设计，只是简单的利用QUARTUES II里的ram-This is a simple memory write VHDL CPU design, does not involve the assembly line design, simply use the ram in QUARTUES II
the-strong-cpu-design
- 增强型CPU设计，带有PC指针与存储器，用VHDL语言写的，不含流水线设计，实现二进制灯循环亮-Enhanced CPU design, with the PC pointer memory write VHDL language, non-pipelined design to achieve binary bright light cycle
traffic-light-design-report
- 交通灯实验报告，内含代码以及详细介绍，容易实现以及理解-The traffic lights experiment report, contains the code and detailed introduction
1M
- 一分频的VHDL程序，内容介绍非常详细，希望能给大家带来方便，很实用的-Divide the VHDL program, introduced in great detail, and the hope that they can bring convenience to very practical
cnt1000
- 一千的计数器vhdl的语言设计，程序简单易懂，易于初学者掌握，希望给大家带来方便-A thousand counter vhdl language design, the program is simple and easy to understand, easy for beginners to master, I hope to bring convenience