资源列表
ISE10.1-introducement
- 文档介绍了使用ISE10.1进行某种功能的FPGA操作步骤，包括从新建文档、综合、功能仿真、编译实现和插入IP核等步骤，讲解非常详细。-Document ISE10.1 introduces the function of some kind of FPGA procedures, including from new document, comprehensive, function simulation, compile realization and insert the IP nucle
FPGA-lessons
- 介绍FPGA系统开发的课件。全国电子竞赛时用的，很实用。-Describes the FPGA system development courseware. National electronic contest, very practical.
ADC12-sampling-experiment
- DC1工作时钟为14Mhz，使用ADC1的通道8来连续转换，并使用DMA来传输转换数据，并在TFT 上实时显示转换数据（显示的是直接读出的ADC规则数据寄存器中的值，即为低12位）-DC1 work for 14 Mhz clock, use ADC1 channel 8 to continuous conversion, and use the DMA to convert data transmission, and in the TFT To convert data on rea
FPGA-ET
- DDS generator programe 产生-DDS generator advanced programe
vgaball
- 用VHDL编写的小球游戏代码，用VGA显示，模块对vga控制器有很好的移植性-Written by VHDL balls of the game code, VGA display, module to the VGA controller have very good portability...
Ultra-9-17
- 超声波流量计采样控制部分的VHDL源代码，基于xilinx的spartan3-The ultrasonic flowmeter sampling control part of the VHDL source code, based on xilinx s spartan3
IEEE-Standard-for-SystemVerilog
- 这是一本systemverilog的标准欢迎下载-This is a SystemVerilog standard are welcome to download
synopsys_verification
- 这是synposys关于systemverilog的使用向导-This is synposys SystemVerilog using the wizard
verilogCRC32
- 32位bit输入的CRC32校验，verilog的代码，以及modelsim的testbench代码-The encode of CRC32 with 32bit-inputs based on verilog, and according encode of testbench
24stimer
- 篮球24s定时器的verilog代码，内涵代码以及程序逻辑说明-basketball 24s timer code of verilog
ICM7242
- ICM7242 代替555和分频器电路。8引脚小封装。-failed to translate
pinlv01
- VHDL实现的数字频率计。频率可到26MHz,精度达到0.001 误差-VHDL frequent