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  1. vhdl-primer-bhaskar

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  2. It s a fundamental book on VHDL primer by Bhaskar...good for final year bachelor s students-It s a fundamental book on VHDL primer by Bhaskar...good for final year bachelor s students...
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-10
    • 文件大小:1.07mb
    • 提供者:aditya
  1. datacompresstion12

    0下载:
  2. jpeg velrilog code its a very good project for mainproject
  3. 所属分类:VHDL-FPGA-Verilog

  1. exp_code

    0下载:
  2. Hi useful exponential code in vhdl
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-14
    • 文件大小:4.65kb
    • 提供者:prakash
  1. fixed_package

    0下载:
  2. Hi useful exponential code in vhdl
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-17
    • 文件大小:23.55kb
    • 提供者:prakash
  1. new_PCI2009-123456ppp

    0下载:
  2. FPGA和PCI9054做的图像采集卡VC测试程序源码,有三种显示模式。-FPGA and PCI9054 VC image capture card to do the test program source code, there are three display modes.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-26
    • 文件大小:8.7mb
    • 提供者:yup
  1. hw1

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  2. Using the schematic Design Entry Method, design a logic circuit that has two 2-bit inputs X and Y, a 1-bit input CinOrBin, and a 1-bit control input SubAddn. When the control input SubAddn is ‘0’, the logic circuit behaves as a 2-bit adder ( X + Y +
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-06
    • 文件大小:356.64kb
    • 提供者:vinay
  1. hw2

    0下载:
  2. Using the VHDL Entry Method, design a logic circuit that behaves a 2-bit adder ( X + Y + CinOrBin ) with carry-in when the control input SubAddn is ‘0’ and behaves as a 2-bit subtracter ( X – Y – CinOrBin ) with borrow-in when the control input SubAd
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-01
    • 文件大小:613.01kb
    • 提供者:vinay
  1. hw3

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  2. Write VHDL codes to model an 8-bit counter that counts every second. It counts from your last two digits of your student ID to your next two digits of your student ID. If the last two digits are greater than the next two digits, the counters counts d
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-16
    • 文件大小:344.44kb
    • 提供者:vinay
  1. hw5

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  2. Design a 2-digit stopwatch that ticks every second. A switch is used to start and stop the time. When the switch is pushed, the time will start and when it is pushed again, the time will stop. In order for the switch to work properly, the switch must
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-04
    • 文件大小:1.31mb
    • 提供者:vinay
  1. hw4

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  2. Write VHDL codes to show, on two 7-segment LEDs, the binary coded decimal (BCD) equivalence of the binary representation of the state of eight switches. Use a function to perform the specified task. Assume that the 7-segment LEDs are turned on with l
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-05
    • 文件大小:323.93kb
    • 提供者:vinay
  1. reg-a-wire

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  2. verilog 使用中reg 与 wire 区别及使用方法-verilog using the difference between reg and wire and method of use
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-13
    • 文件大小:1.51kb
    • 提供者:张树强
  1. main

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  2. 基于FPGA的驱动诺基亚3310显示器驱动程序,模拟SPI传输模式-FPGA-based Nokia 3310 display driver drivers to simulate SPI Transfer Mode
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-08
    • 文件大小:1.23kb
    • 提供者:吕念
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