资源列表
Modelsim_Advanced
- 介绍modelsim的使用说明，文字浅显易懂-modelsim user guide
tri-state-bidirectional-bus
- FPGA中三态双向总线的实现。以一个实 际工程中的程序来详细介绍三态双向总线实现及应用。-Implementation of FPGA in the tri-state bidirectional bus
sinewave-case
- 利用verilog语言以及case语句实现正弦波波形，并利用modelsim完成波形仿真。-Use verilog language and case statement to achieve sinusoidal waveform, and use modelsim complete waveform simulation.
spi
- VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the \"master\" and the \"slave\". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits
machine
- microprocessor in vhdl
24stimer
- 篮球24s定时器的verilog代码，内涵代码以及程序逻辑说明-basketball 24s timer code of verilog
3-to-8Decoder
- 3 to 8 Decoder in vhdl
xilnx_sata
- xilinx 的sata解决方案，已对其中内容作了修改，可实现综合-sata the xilinx solutions have been made to amend the contents of which can be used
uart
- 利用xilinx 公司的ise软件基于verilog HDL实现UART控制程序-based on the xilinx ise and use verilog HDL language to achieve the purposes that control the uart.
lift_syn
- 实现简易4层电梯控制核心模块，完成了电梯上下层控制、指示灯显示、优先级判断等多种常用功能。-The realization of simple 4 layer core elevator control module, the completion of the elevator on the lower control, indicator light shows that determine the priority and many other commonly used function
RecoveryRemoval
- 关于FPGA中的timequest timing analyzer中的recovery 和removal的讲解-On the FPGA in timequest timing analyzer in the recovery and removal of the explanation
uart
- Atmega 328 UART clone with testbench, cannot be synthesized to gates