资源列表
Serial_port_modul
- 串口通讯的Verilog程序，用于FPGA控制串口进行数据发送，接收，包含一个串口模块和一个进行调试的主控模块，主控模块可以随意自我设置，串口模块是固定的，全部程序都经过调试，都带有注释，很清晰。-Verilog serial communication program for FPGA control serial data to send, receive, including a serial debugging module and a control module, control m
QAM
- its about how to impliment qam on fpga
COlD_FFT
- The VHDL implementation of 8-point FFT in VHDL. Radix 2 Decimation in Frequency-The VHDL implementation of 8-point FFT in VHDL. Radix 2 Decimation in Frequency It is very good
shzzh
- 这是在FPGA上实现的数字钟功能，用VERILOG语言编程，已功过编译，仿真验证-This is the FPGA to achieve the digital clock function with verilog programming language, compiler has merits and demerits. Simulation
2402-dld
- Multisim® is a schematic capture, simulation, and programmable logic tool used by college and university students in their course of study of electronics and electrical engineering. Multisim is widely regarded as an excellent tool for classroom a
CAN_controller_ip
- 一个用硬件描述语言编写CAN总线控制器的IP，可以用在NIOS II上。
Arm7_Verilog
- 基于Verilog的Arm7系统构建代码。-System Verilog for Arm7 based construction code.
EPM7032-ENCODE
- ALTETRA EPM7032 ENCODE正反轉16位元輸出+14輸入+內碼-ALTETRA EPM7032 ENCODE
xemac
- xilinx fpga xemac网卡驱动-xilinx fpga xemac card driver
Synplify
- 华为synplify入门教程：Synplify快速入门-Huawei Synplify Tutorial: Synplify Quick Start
S5_BOARD_ID
- 1、程序是7段扫描显示器的扫描输出的例子 2、利用扫描原理4个数码管显示4个不同的数字，但是数据输入是一组总线, -1, the program is the 7-segment display of the scan output scans example 2, using the scanning principle four digital display four different figures, but the data input is a set of bus
FPGA-FIR
- FIR滤波器，算法，采用VHDL编程语言，算法比较简单，希望对大家有所帮助。-FIR filter algorithm, using VHDL programming language, the algorithm is simple, we want to help.