资源列表
en.SPI_EEPROM_Verilog_models_V10
- spi接口的eeprom模型，型号为st公司m65pxx(The eeprom model of spi interface is st company m65pxx)
JK_F_F
- This a VHDL code for J-K flip flop-This is a VHDL code for J-K flip flop
dqpsk_demodulator_f_pa
- FSK QPSK DQPSK 等verilog 源码 及asic实现-FSK QPSK DQPSK and asic implementation such as verilog source
subway7
- 本实验是基于VHDL设计一个地铁自动售票系统。该系统能一次出售最多9张票，并实现找零、显示、出票、取消等功能。划分为控制模块、计算模块、分频模块、出票模块、显示模块等5个功能模块。-The experiment is based on the VHDL design a subway automatic ticketing system. The system can be a maximum of nine tickets sold, and to achieve homing, show t
RGB-to-YCbCr[Verilog]
- 基于FPGA平台的颜色色彩空间转换 RGB to YCbCr-Based on the FPGA platform color RGB to YCbCr color space transformation
NIOSII_Other_Tools
- NIOS II研究开发者使用手册,其中讲述了一些实用工具的说明。-NIOS II research and development to use the manual, which describes some useful tools for descr iption.
Assembly-code-examples-of-msp430f448-(CCE)
- The assembly language program code examples for MSP430f448 and Msp430f438 are described in this zipped file. The easy understanding of simple uart, adc, watchdog,timer program are included
12
- SIGMA DELTA MODULATOR
fsk
- vhddl implementation of frequency shift keying
EP1C3_12_3_VGA
- vga在vhdl下的 图像控制 一种方法-vga vhdl
opencores_can
- CANIP核 CAN总线以报文为单位进行数据传送,报文的优先级结合在11位标识符中,具有最低二进制数的标识符有最高的优先 级。-CANIPCore
VGA_Controller
- 适用于 Microtronix 的 Lancelot card 的 IP CORE-Microtronix of Lancelot card IP CORE