资源列表
send
- 通过先对异步串口发送模块的编写对其验证，再联合接收模块实现串口的收发-At frist,checking the module of UART s sending function,then link the recive module to realize reading and writing
ALU
- 这是一个quartus语言编写的运算器，可以通过简易的四则运算。-This is the of quartus language of operator, by the simple four computing.
cpu
- 这是一个quartus语言编写的单周期cpu，可以进行运算、存储等功能。-This is a quartus language of single-cycle CPU, computing, storage and other functions.
ARM32
- 这是一个quartus编写的arm结构的桶形移位器，可以进行移位运算。-This is a the quartus write the arm structure of the barrel shifter, can shift operation.
ttytest
- S3C6410 uart3的读写操作，包括比特率等的设定-IO on UART3 of S3C6410
JTD
- 基于verilog的交通灯，倒计时并具有动态显示功能。红灯结束后黄灯闪烁5s,stop为高电平时，数码管闪烁并禁止通行-traffic light with a function of displaying and counting.
Verilog--classic
- verilog 的经典教程，包含基本命令定义等内容并且由实例讲解了具体的编程方法和设计思想-Verilog classic tutorials, include basic commands the content such as defined by example and explain the specific programming method and design thought
retiming
- 这篇文章讲述了register retiming技术.这项技术是设计VLSI必须要掌握的技能，另外在基于FPGA设计中，register retiming可以使系统频率上升，提高吞吐量。-This paper describe a register retiming mode for VLSI and FPGA-based design. This mode adopted for design can enhance system throughput and increase system
Detecta_Header
- Detect header 7EH in a serial communication
FSM_Recepcion
- Finite State Machine to receive data froma pc ina serial communication-Finite State Machine to receive data froma pc ina serial communication
LFSR
- Linear Feedback Shift Register created to generate random numbers
Prueba_RS232
- Its only a schematic of probe to complete the sending of data through rs232