资源列表
CU-RAM-CODES
- CU RAM VHDL codes for spartan 3E board
CCDII
- VHDL编写的线阵CCD驱动源代码，稍作修改适用于大多数线阵CCD。-CCD driver source code, minor modifications apply to most of the linear array CCD.
MUX4x1
- Mux4x1 Verilog code for Xilinx Spartan 3E board
Decoder-3x8
- Decoder 3x8 Verilog code... This is for Xilinx Spartan 3E board
ControlUnit
- Control Unit VHDL code. Xilinx Spartan 3E board
ClockGen
- ClockGen code in VHDL for Xilinx Spartan 3E board
JTAG-Engine
- A source code for JTAG access.
FPGAkeshe.doc
- 基于FPGA/CPLD的以QUARTUS2 的能够实现交通灯的显示与控制-enable the lingting traffic display
singlePcyclePMIPS2
- 多周期MIPS实现的CPU设计方案，包括源码-MIPS multi-cycle
Spantan3EIP
- 在spantan 3e实现仿真，已经验证了-Spantan 3e simulation, has been verified
CPLD
- 使用CPLD扩展I / O，控制所有输入和输出引脚读写操作，以及对各片选信号的控制。-The CPLD is used to expand the I/O control read and write control of all input and output pins, as well as the chip select signal.
library-ieee
- Look up table in vhdl