资源列表
NIOS_IIuart_program
- 对于初学者是很好的资料，教你如何从串口来熟悉nios ii。-NIOS II Step by Step7 uart raw program and Nios II Device architecture
fpga-ir-image-processor
- 基于FPGA的直方图投影增强算法主要讲述的是红外的图像处理算法。很有借鉴意义。-Abstract：Amid uFPA therrnal imaging equipment，to obtain clear infrared image，people need to ve hetemgeneity adjust and Blind Pixels fil1 t0 f0cal plane device．
OFDM_code
- ofdm implementation in Verilog
fenpinqisheji
- 设计的是一个带复位的分频器，输入时钟为60MHz，输出时钟为7.5MHz。经过quartusII仿真过了的-The design is a reset of the divider, the input clock is 60MHz, the output clock is 7.5MHz. After quartusII simulation over the
jishuqizhouqixingxieshixu
- 利用计数器控制状态变更产生周期性写时序 ，50MHz的晶振频率，可以产生50MHz的计数器。每个计数周期代表20ns。 每毫秒产生一个写脉冲，意味着20000个时钟为一个大循环，换成二进制，需要15位的计数器，计到19999强制归零。 不可能产生30ms的准确写宽度，最小只能用两个周期产生40ms宽的写脉冲。-The Cong ℃ of the LIU ╃ using Counters ㄦ with Liu chop Yan Gao Huoguo spin Chui Hai the Uu
testUSART
- 将一块板的发送并口转为串口，完成两块板的通信-Will the board parallel port to send a serial port, complete two boards communications
1_ADDER
- ＣＰＵ内部的加法器用ｖｈｄｌ语言在可编程逻辑器件上的实现-Within the CPU is VHDL language addition in programmable logic devices for fulfillment
4_COMP
- ＣＰＵ内部的比较器用ｖｈｄｌ语言在可编程逻辑器件上的实现-The comparison of the CPU internal used VHDL language in programmable logic devices for fulfillment
hongwai
- 红外协议代码用ｖｈｄｌ语言编写，在可编程器件上实现-Infrared agreement with VHDL code language, in programmable devices realize
key
- 在可编程器件上实现的按键显示的ｖｈｄｌ语言的代码-In programmable devices realize in programmable devices on the realization of the buttons on the display of code language VHDL
verilog_behavioral_modeling
- Verilog behavioral modeling
KEY_SMG
- 嵌入式FPGA中的nios ii例程。输入按键，数码管显示相印的数字-Embedded in the FPGA nios ii routines. Input buttons, digital pipe display in the digital printing