资源列表
rom_in
- Altera FPGA rom 写入代码-Altera FPGA ROM writing code
rom_mod_sine
- Altera FPGA 从rom读数据，产生正弦波，modulsim仿真-Altera FPGA read data from ROM, produce sine wave, modulsim simulation
rom_read_modelsim
- Altera FPGA ，modulsim仿真rom读取，Quartus工程-Altera FPGA, modulsim simulation ROM read, Quartus engineering
mdio_slave
- It s VERILOG (not VHDL) code for mdio slave
width
- 用verilog编写的，通过对时钟脉冲计数来记录脉冲宽度-measure pulse width
pulse_width
- 用verilog编写的，通过对时钟脉冲计数来记录脉冲宽度-measure pulse width
clock
- 本设计主要研究基于FPGA的数字钟，要求时间以24小时为一个周期,显示年、月、日、时、分、秒。具有校时以及报时功能，可以对年、月、日、时、分及秒进行单独校对，使其校正到标准时间。-This design is the main research based on FPGA digital clock, required time to 24 hours for a cycle, display date and time, minutes and seconds. The strike has
VerilogHDLshuzizhong
- 本设计的数字钟,要求显示格式为小时—分钟—秒钟，分别在8个七段LED数码管上以动态分时扫描的方式显示，附加功能：有调时模式，增加秒表功能-The design of the digital clock, required to display format for hours-minutes-seconds, respectively in eight seven LED digital tube for dynamic points the way to scan showed that ad
myprogram
- 文件包中包含了与FPGA及串口通信相关的程序及教程，对学习FPGA很有帮助。-File packages that contain and FPGA and serial interface communication related procedures and tutorial to the study of FPGA to have the help very much.
addN
- A simple ADDN module
FREQ
- 该程序使用verilog编程语言，实现了频率计-The program use verilog programming language, realized the frequency meter
Embedded_System_Lab
- Tutorial on Embedded Systems with NIOS II, SOPCBuilder and Quartus II.