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  1. 34105908-Multipliers-Using-Vhdl

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  2. ABSTRACT: Low power consumption and smaller area are some of the most important criteria for the fabrication of DSP systems and high performance systems. Optimizing the speed and area of the multiplier is a major design issue. However, area and
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-17
    • 文件大小:371.41kb
    • 提供者:phitoan
  1. 38504873-pll

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  2. Introduction In 2004 Octavian Florescu created the UW ASIC group. At that time, the analog subgroup of the UW ASIC group was involved in the design of a PLL. The topology of that PLL, which is now referred to as Phase Locked Loop Version 1, i
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-16
    • 文件大小:358.19kb
    • 提供者:phitoan
  1. 40716003-VHDL

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  2. What is VHDL? • VHDL stands for VHSIC Hardware Descr iption Language. • VHSIC is an abbreviation for Very High Speed Integrated Circuit, a project sponsered by the US Government and Air Force begun in 1980 to advance techniques
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-16
    • 文件大小:85.5kb
    • 提供者:phitoan
  1. 44317447-Vhdl-Sim-Syn

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  2. This document is meant to be an introduction to VHDL both as a simulation language and an input language for automatic logic synthesis. It is based on material originally prepared for the ASIC Design Laboratory taught at the University of Twente
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-16
    • 文件大小:106.51kb
    • 提供者:phitoan
  1. hidoh

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  2. 汇编计数器,可以在计算机上直接运行的软件程序-Compilation of the counter, you can run directly on a computer software program
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-15
    • 文件大小:6.25kb
    • 提供者:shjt
  1. rk

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  2. this code is Universal Asynchronous Transreciver this project is IEEE 2008 standard this project is done by my personal and i had verilog code.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-20
    • 文件大小:5.67mb
    • 提供者:chandu
  1. HDB3_encoder_QuartusPrj

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  2. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-30
    • 文件大小:12.58mb
    • 提供者:张昕
  1. MIT[1].Press_.Circuit.Design.with.VHDL._2004_.TLF

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  2. This verilog vending machine code. We can eat beverage and soda with only $1.25-This is verilog vending machine code. We can eat beverage and soda with only $1.25
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-17
    • 文件大小:4.82mb
    • 提供者:Psycho
  1. server

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  2. This verilog vending machine code. We can eat beverage and soda with only $1.25-This is verilog vending machine code. We can eat beverage and soda with only $1.25
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-05
    • 文件大小:1.33kb
    • 提供者:Psycho
  1. vending

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  2. This is verilog vending machine code. We can eat beverage and soda with only $1.25 This decribes all schematic and state diagram. Ducksooyo~
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-08
    • 文件大小:110.2kb
    • 提供者:Psycho
  1. Design-AND-gate

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  2. 通过应用QUARTUSII开发软件对与门的设计(二输入)和D触发器的设计。 -QUARTUSII development through the application of software and door design (two inputs) and the D flip-flop design.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-04
    • 文件大小:1.78kb
    • 提供者:renee
  1. Multiplexer-Description

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  2. 通过应用QUARTUSII开发软件对二选一多路选择器进行设计并运行结果-Software development through the application of QUARTUSII choose one of two multiplexer design and operation results
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-01
    • 文件大小:10.14kb
    • 提供者:renee
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