资源列表
Digital-IF-and-FPGA
- 用 FPGA可以使符合标准的系统有别于竞争对手的产品，同时还为应用获得最佳平衡。-Digital IF and FPGA
fpga2
- an artical about controller area protocol and fpga device that i found on the net.
ep1c12_32_vga
- 完整的VGA时序及其彩条显示，棋盘格显示，注释完整-Complete VGA timing and color bar display, checkerboard display, annotate complete
part2
- Altera DE2 开发板试验3 第2部分VHDL答案-Altera DE2 Lab3 Part2 VHDL Answer
display_fsm
- 采用状态机移位显示字符的VHDL代码，包括QUARTUS2的完整工程。-Shifting display with state machine . VHDL code , including the complete QUARTUS2 project.
ADD
- VHDL开发入门程序，比较简单但是可以形成有效的VHDL开发习惯 -Introduction to VHDL development process is relatively simple but can be used to form an effective VHDL development
jiaotong
- 交通灯控制器的VHDL设计,能控制十字路口的红绿灯转换,通过目标芯片EPF10KLC84-4验证
digitalclock
- 用FPGA实现的数字时钟功能-Implemented using FPGA digital clock function
coder83
- 基于VHDL的8-3优先编码器模块，din0-din7八位二进制输入编码后输出三位编码结果。采用正逻辑设计，高电平有效。-8-3 priority encoder module, based on VHDL din0- din7 eight binary input encoded output three coding results. Adopt positive logic design, high level effectively.
100vhdl_project
- 熟悉VHDL语言的小程序和.pdf文档，例如：乘法器、比较器和交通等设计等100个小例子，非常适合初学者。-Familiar with the VHDL language, applets and. Pdf documents, such as: multiplier, comparator and transportation design 100 small example, very suitable for beginners.
cpld-urat-vhdl
- 基于CPLD的VHDL UART代码，串行异步通信，含代码及仿真图-Based on the CPLD VHDL UART code, serial asynchronous communication, including code and simulation diagram
HighSpeedParallelMultiple
- quartus II 下VHDL实现快速乘法器-quartus II VHDL High Speed Parallel Multiple