资源列表
lab2
- 算数逻辑运算单元 使用verilog编写(Arithmetic logical arithmetic units are written in Verilog)
dianzhen
- 8位渐变色点阵的VHDL实现，在单片机中进行过仿真-8 gradient lattice of VHDL, simulation conducted in SCM
verilog
- 数字信号除了的FPGA实现的Verilog源代码，之前发过一份是VHDL，各有所需吧，需要的看看吧-Digital signal in addition to the realization of the FPGA Verilog source code, send before a is VHDL, each have need it, need to look at it
bin2bcd7seg
- 用vhdl语言编译一个码制转换 四位二进制->BCD码，然后将BCD码->七段显示器码。 （1）当输入为0~9的数时，其十位数为0，个位数=输入。 当输入为10~15的数时，其十位数为1，个位数=输入-10。 （2）然后将十位和个位的BCD码转换为七段显示码 -Vhdl language used to compile a binary code system conversion of four-> BCD code, then BCD code->
FPGA-source-code-in-IRIG_B-Design
- FPGA在IRIG_B码源设计中FPGA source code in IRIG_B Design-FPGA source code in IRIG_B Design
100VHDLexample
- VHDL编程中常用到的100个例子的源程序包括四输入多路器，信号驱动源，寄存／计数器等，使用非常方便。-VHDL programming of commonly used example of the source 100 includes a four-input multiplexer, the signal driver source, storage/counter, etc., very convenient to use.
OpenSpacewire_090406.rar
- SpaceWire节点逻辑，VHDL，希望有帮助,SpaceWire Node logic, can be used widely
VGA_STUDY--OK
- VGA 测试程序，可显示彩色条纹，用vhdl语言编写，经过测试，运行稳定，带有注释！
BPSK
- 在quartus ii下完成的用VHDL语言编写的数字式调频BPSK的调制，其中DDS和成型滤波使用ip核完成-Accomplished in quartus ii the use of VHDL language digital FM BPSK modulation, which use the ip filter DDS and forming complete nuclear
3D_Models_Convertor
- 3D Models Convertor 3D Models Convertor-3D Models Convertor 3D Models Convertor 3D Models Convertor
20161122_ff
- MD5认证部分的第一轮中包含F函数的一次操作的FPGA实现源代码，采用Verilog，在Quartus II上综合-MD5 authentication part of the first round contains an F function of the operation of the FPGA implementation of the source code, using Verilog, integrated in the Quartus II
clock
- 时钟设计 实现钟表功能可自动调节时间的大小以及充当秒表-Clock design and implementation of time clocks feature automatically adjusts the size and act as a stopwatch