资源列表
full_adder
- 用verilog在半加器的基础上实现了全加器，方法简单巧妙，对于FPGA入门学习很有帮助-In the half adder using verilog on the basis of a full adder, simple and clever, very helpful for the FPGA Starter
cordic_SINE_COSINE_code_vhd
- 首先采用cordic坐标旋转数字计算法推导求解三角函数的有效算法，然后利用小角度时的三角函数倍角公式推导有效的三角函数Cos,Sin 求解方法。-First use of cordic CORDIC trigonometric calculations derived an effective algorithm to solve, and then use the small angle formula of trigonometric double angle trigonometric f
typewriter
- typewriter, shows characters on lcd about the keys from the de2 board.
DAC
- DAC spartan 3e starter
MPIS_singlecircle-12-12-completed
- MPIS单周期指令集，用VHDL编程，能够执行16条指令-MPIS single-cycle instruction set, VHDL programming instructions to perform 16
ADCODE
- 用FPGA控制双ADC0809读写，用于双AD热备控制，用verilog实现-FPGA control with dual ADC0809 read and write, hot standby control for double AD, with verilog implementation
music.v
- 用VHDL硬件描述语言在CPLD实现播放音乐-VHDL hardware descr iption language used for playing music in the CPLD
lab3_group27
- 数字电路的基本门，有register，fulladder，还有一个洗衣机的控制程序-The basic digital circuit gates, register, fulladder, there is a washing machine control program
cpu
- 简单的cpu，以verilog语言写的，希望大家能提点意见。-Simple cpu, the verilog language to write, and I hope we can Tidianyijian.
verilog_testbench_genetator
- 这是一个perl程序 只需要在cmd中运行，参数为你的Verilog名字 功能是:半自动生成Verilog的testbench，提高编码效率-#-----READ ME of verilog_tb_generate.pl----------------------| # | #-----copyright(C) Xzmeng 2010---------------
WATERMARKING_FPGA_BITSTREAM_FOR_IP_PROTECTION
- WATERMARKING FPGA BITSTREAM FOR IP PROTECTION
CPLD_FPGA
- 卡内基梅陇大学课程讲卡内基梅陇大学课程讲义-Carnegie Mellon University, Carnegie Mellon University about verilog verilog course lecture notes