资源列表
Xilinx_FPGA_design_tips
- 华为FPGA设计高级技巧Xilinx篇 华为FPGA设计高级技巧Xilinx篇-Xilinx FPGA design tips for Huawei Huawei articles Xilinx FPGA design article advanced techniques
SystemVerilog
- 关于SYSTEMVERILOG的语法，一些例子-About SYSTEMVERILOG syntax, examples and so on. . . . . . .
stratixIII_3sl150_dev_TSE_SGMII_v1
- 该程序实现altera开发板 stratix III 3S150通过以太网与pc之间通信。 使用Quartus II和Nios II 设计。 因为altera官方没有这块板子的正确网卡与pc通信的程序，-Overall This example works at 1000M/100M/10M Base SGMII mode on SIII 3S150 Kit. Designed by Quartus II/IP Cores/Nios II EDS v8.0 This is not
Luckey
- VHDL 频率可变的任意波形发生器-vhdl pinlvketiao renyiboxingfashengqi
ff
- 简单的网站 一个网站 很简单。 我自己写的。写了一会儿哟-something
MulticlockCPU.tar
- verilog hdl实现多周期CPU，按照有限状态己设计，含源码、实验报告和详细vsd电路图-verilog hdl multi-cycle CPU, in accordance with the finite-state has been the design, including source code, test reports and detailed schematic vsd
ARMinstructions.pdf.tar
- ARM汇编指令集详解,包括ARM7架构和大部分汇编指令，宛城布衣整理-ARM instruction set Detailed assembly, finishing Wancheng commoner
ad0809VHDL
- ADC0809控制程序，用VHDL语言实现，简单实用，已通过硬件测试-ADC0809 control procedures, using VHDL language, simple and practical, has passed the hardware test
verilog
- 无线通信用verilog代码，超全，可用来做基本设计-Verilog code for wireless communications, ultra wide, can be used for basic design
Q8051
- A 1T51 core which contain 16 verilog files. this mcu core consiste with standard 51
ep1c12_29_dds
- 基于周立功SOPC实验开发平台，利用VHDL语言，实现DDS调频-Zhou, who based SOPC experimental development platform, using VHDL language, to achieve DDS FM
Group27_lab5
- VHDL的基本门，ram，rom等的实现-VHDL basic door, ram, rom, etc. to achieve