资源列表
Verilog
- 王金明版的verilog HDL的135个经典设计实例-Wang Jinming version of the Verilog HDL 135 classic design example
31-LED
- led控制流水动作来实现单片机的功能实现，进行软件仿真-to control led function
Sdram_Control_4Port
- Sdram Control 4Port Sdram Control 4Port
FIFO_TD
- FIFO的VHDL测试程序,在Modelsim下完全可以运行-The test_bench of fifo
Count-of-29-hex
- 29进制的计数期，vhdl实现，在quartus里编译成功-Count of 29 hex, the VHDL implementation, compiled in quartus success
Mode-variable-counter-vhdl
- 模可变计数器 vhdl实现 quartus编译通过-Mode variable counter vhdl achieve quartus compiled by
liushuideng-6
- 可通过按键改变模式的流水灯vhdl程序 quartus编译通过-Button to change the mode of light water VHDL program quartus compiled by
p_dect--5
- 奇偶检测器 vhdl实现 quartus编译通过-Parity detector the vhdl realize quartus compiled by
IDT
- IDT频率综合器接口程序和应用实例，外加IDT的行为模型-IDT frequency synthesizer interface program and application examples, plus a behavioral model of the IDT
ps2
- PS/2鼠标接口状态机的VHDL语言描述-VHDL descr iption of the PS/2 mouse interface state machine
FSM-verilog
- 自己写的 FSM verilog代码 ，参考The Verilog Hardware Descr iption Languag-an example of Fsm written with verilog
TURBO_2964
- 本程序只进行了2964 帧长的TPC编码-CtransfDlg::OnEncodeTPC2964(CString SrcFile,struct PARAMETER*PARAMETERDEAL)