资源列表
exer_vhdl_PWM
- 具有微处理器接口的PWMSG，周期和占空比均可调，感兴趣的可以自己扩展其他接口-Microprocessor interface PWMSG, period and duty cycle can be adjusted, interested can extend other interfaces
DSP_EMIF_if
- fpga的emif的设计与开发的源代码-source code the fpga emif, design and development! ! ! !
h.264
- 包含h.264的包括帧内、帧间、变换编码、熵编码的vhdl源程序-Contains the vhdl source h.264 frame, frame, transform coding, entropy coding
acc8
- VHDL语言设计八位加法器，可用于CPU中的加法模块，-VHDL language eight adder, adder module can be used for the CPU,
8weicpu
- VHDL语言设计的8位简单的CPU，可以实现包括加法，减法，移位操作，赋值，自加等十多种基本的操作-8 of the VHDL language simple CPU, you can achieve more than 10 kinds of basic operations including addition, subtraction, shift operations, assignment, since Canada
12
- 单片机用1602 lcd与ds18b20设计的温度报警器程序，虽不可仿真，但可参考-Canopy temperature control system design and implementation
logic_analysis
- 逻辑分析仪设计，完成了数据采样，VGA显示控制，请大家使用-logic analysis
LED_ontrol_VHDL
- 基于FPGA的LED控制电路设计资料（VHDL程序）-LED control circuit design information (VHDL)
MFSK_modulation
- 基于VHDL的mfsk调制电路设计（VHDL源程序）-Based on VHDL mfsk modulation circuit design (VHDL source)
RobustVerilog_free1.2_win
- RobustVerilog生成verilog工具-RobustVerilog version
leading-zero
- 对于32位寄存器前导零个数的计数，一个简单的程序-32 registers a leading zero number of counts, a simple procedure
DDS
- dds的源码，可以合成任意波形，VHDL语言-dds source, we can refer to very good