资源列表
jsq
- 包括异步计数器，序列码发生器，两个程序都可以运行-Both programs can run asynchronous counters, serial number generator,
filter_512
- FIR低通滤波器 veilog源代码 参数自行调整可实现带通，低通，高通-FIR low pass filter
ActelFPGA_RAM_an
- FPGA下开发RAM的手册，与FPGA自带的说明不同-FPGA development manual of RAM, comes with instructions and FPGA
sd_photo
- 简易电子相册。可以认为自由控制图片的显示方式。-Simple electronic albums. That the freedom to control the picture display.
data-acquisition-system
- 压力信号0~102kg，经过模拟调理电路变为0~5v电压信号，通过键盘按键在数码管上显示-Pressure signal 0 ~ 102kg, after the analog conditioning circuit becomes 0 ~ 5v voltage signal via the keyboard button on the digital tube display
09_uart2
- 串口字节收发通信，可以从PC机上通过串口调试助手输入一个字节然后从串口调试助手的接收区查找你输入的字节-Serial bytes to send and receive communication from the PC through the serial port debugging assistant enter a byte and then find your input bytes from a serial debugging assistant reception area
10_ps2_keyboard_test
- ps2键盘输入测试程序，verlog代码实现-ps2 keyboard input test program, verlog code to achieve
led_nios2_control
- 利用noise核，控制LED灯的亮灭，altera系列FPGA的SOPC设计程序。-Noise core, to control the LED light bright off the the altera series FPGA and SOPC design process.
test_uart2
- 可以实现串口收发，能够通过数码管显示从PC机上输入的数据-Serial transceiver, the number of input data from the PC through the digital display
read_file_test
- VHDL读写文件范例，仿真专用，验证通过-Examples of VHDL to read and write files, simulation-specific, verified by
uart8bit
- 串口通信verilog ml605开发板实现代码-Ml605 development board, serial communication Verilog code
my_apll_calcoeff
- 在设计锁相环时，二阶环路滤波器的系数设计极为重要，本程序可以用于FPGA设计锁相环时计算所需的参数。-It is important to calculate a tow order loop filter,when designing a phase locked loop.This program can be used in designing a phase locked loop based FPGA or DSP directly.