资源列表
Q
- 高级FPGA 教学实验平台实验指导书－逻辑设计-Advanced FPGA teaching experimental platform for experimental instructions- logic design
module-ad
- AD控制程序,基于Verilog语言来编写程序代码.-AD control program based on the Verilog language to write code.
debug
- 基于LEON3的片上网络调试系统和相关的技术资料-The LEON3 the network on chip debug system and related technical information
div
- 一分频，通过计数器原理得到的一分频。十分简洁，适合初学者-A divide, a divide counter principle. Very simple, suitable for beginners
8-Bit-Simple-Up-Counter
- 简单的，计数器，上升沿有效。经过ise13.1测试，完全符合逻辑-Simple, counters, and the positive edge. Tested
8-Bit-Up-Counter-With-Load
- 8位计数器，能实现加减计数，经过ise 测试仿真了。符合逻辑-8-bit counter, plus or minus count after ise test simulation. Logical
Divide-by-2-Counter
- 2分频，通过计数器实现，很实用的，可以作为时钟驱动。-Divide by the counter to achieve very practical, can be used as clock driver.
Gray-Counter
- 格雷码，用于理解格雷码的的功能，减少出错。同样对于卡诺图很用吧。-Gray code, Gray code, the function used to understand and reduce errors. The same for the Karnaugh map.
sdram_mdl
- SDRAM的FPGA 工程。用Verilog编写。器件型号为K4S641632，经过实验板验证，绝对可用。-SDRAM FPGA project. Written in Verilog. Device model K4S641632, after the experimental board, absolutely available.
verilogiic1121
- I2C总线的FPGA工程，Verilog编写。是测试过的程序，绝对可用。-I2C bus of the FPGA project, Verilog prepared. Program is tested, absolutely available.
JXJ_TOP
- 用VHDL语言建立的简单计算机工程，经测试可以正确。-VHDL language to establish a simple computer engineering, has been tested correctly.
ps2verilog
- PS2接口的FPGA工程，经过测试，绝对可用。-PS2 port of the FPGA project, after testing, is absolutely available.